May 222011
 

Dear readers, I would like to welcome Tauseef Rab as a guest blogger. Tauseef has extensive experience in logic design and circuit design, having worked in companies like Freescale, SigmaTel, Marvell, and Qualcomm. While my post covered topics from several fields, I agree with Tauseef that most interviews are more targeted to a specific topic. On my request, Tauseef has agreed to share a list of questions he finds most relevant for logic design. Tauseef, I look forward to your contributions in the future as well.

I think you should split your post [Ten fun hardware design questions] into two very relevant, yet unique topics: circuit design (transistor level) and logic design.

Following are the Top 7 Logic Design review topics in my mind (I will share the circuit design review sheet later).

1. State Machines. Being able to capture control events in a state machine is absolutely a key. Also be sure you know how to take a state machine and write HDL code.

Q) Detect a sequence of 110101. Make the output optimal for timing (think mealy/moore).

2. Gate Level design. Knowing the levels of logic can help one think ahead and be on the look out for potential timing paths. A second benefit is that it helps with ECO process. Knowing Karnaugh maps is also a key.

Q) A typical question is to solve a K-Map. For ECO related questions, the key is to know DeMorgan’s law.

3. RTL: Know how to code in at least one popular HDL (verilog, system verilog, VHDL)

Q) You should be able to code any combinatorial logic (most commonly asked is a mux). Moreover, you should be able to use the mux’s output signal as a D input and write code to capture it in a rising edge asynchronously reset-able D flip flop.

4. Timing. A good logic designer very often finds himself dealing with primetime reports and trying to fix max and min delay issues.

Q) Perform setup/Hold time calculations. Also, know how skew changes the equation. Which (setup/hold violation) is a harder problem?

5. Power. Low power techniques are not just desired but required in cutting edge designs. You should know clock gating and data gating.

6. Tools: This includes familarity with industry tools and scripting, e.g., Formality/Conformal LEC (for Formal Verification), Magma/Synopsis synthesis, timing, floor planning tools, and Tcl scripts to set up these tools.

7. Basic verification. Writing assertions, and knowing how to do basic debuging in a used simulator (verdi, questa-sim)

 

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