May 242011
 

Dear readers, I recently got introduced to XMOS and the concept of open hardware thanks to Jonathan May. I got curious about XMOS when Jonathan responded to one my posts as “for proper multicore, look at @xmos.” I do feel that it’s a concept we should all be aware of.

On my request, Jonathan has written a wonderful introduction to XMOS specifically targeted to our audience with combined hardware/software focus. I hope you will enjoy this post. You can follow Jonathan at @jonathan_may.

Trends

Moore’s Law trends have driven the microelectronics industry for 30 years. Whether they will end at some point remains the subject of intense debate, but one fact is certain: we are now seeing a decreasing return on investment in additional silicon area – the “low-hanging fruit” (e.g. bigger caches, better branch prediction) were eaten many years ago. Now the question is – if you double the available area on a die, how should it be used?

The other major trend that has been driving the industry is the tightening strain that has been put on new product development. Market cycles are shortening and performance demands are increasing. Creating new ASICs or SoCs incurs both design/manufacture and time costs that are past the point of economic viability for all but the biggest market products.

So where can embedded engineers now turn?

Where Trends Meet

The answer lies in general-purpose programmability. The proliferation of ARM cores across the embedded product spectrum is a testament to this fact. But ARM cores only offer half the solution – they handle high-level user software, not low-level hardware protocols. Today, it is not only GUIs that change on a product-by-product, or upgrade-by-upgrade basis. It is the hardware protocols themselves – audio/video protocols, motor controllers, USB, AVB, etc. These changes have traditionally been made in hardware, and required chip re-spins!

Enter XMOS…

XMOS has created a technology that sits at the point these two trends meet:

1. XMOS makes hardware programmable – enabling designers to implement timing-critical interfaces such as USB in software, Ethernet in software, SPI/UART in software, whilst also running high-level user code. What’s more, the architecture is optimized to perform DSP-like functionality too. This means designers no longer need a chip re-spin for a new product – just a software rewrite and a board re-spin, lowering the redevelopment time and cost by several orders of magnitude.

2. XMOS makes good use of additional silicon – the XMOS architecture employs simple, pipelined, hardware multithreaded (HMT) cores – with up to 8 hardware threads. These cores have high-speed, low-latency “ports” – effectively programmable, buffered pins that can be accessed directly from high-level languages. Chips containing 1, 2, or 4 cores are currently available matching the processing requirements of a variety of applications without changing the development flow.

Much like the INMOS transputer of the 1980s, the XMOS cores employ CSP-like semantics, with channels (implemented natively in hardware) used for communication and synchronization between threads in a safe and deterministic manner. Channel communication is universal: a thread on one core can communicate with a thread on a different core, chip, or board in exactly the same way as if it were a local thread, on the same core. These primitives permit safe, scalable concurrency – and eliminate the conventional (but mistaken) arguments that “parallel programming is hard”.

Ultimately, the real magic lies in the coupling of HMT with direct software control over pins. Round-robin scheduling means that each hardware thread can be considered its own processor, with a guaranteed “MHz”, which makes programming timing-critical interfaces simple – no need to worry about interrupts, memory latencies or other sources of non-determinism. It is this combination that permits multiple timing-critical hardware interfaces to be created in software and executed on the same core!

Here is a simple UART transmitter, written in XC, as an example. It demonstrates the use of ports and timers (timers are another primitive built-in to the core to enable the definition of hardware in software) – within a conventional C-like syntax. For full documentation, please read the XMOS manuals at http://xmos.com

# include <xs1.h>
# define BIT_RATE 115200
# define BIT_TIME 100000000 / BIT_RATE

out port TXD = XS1_PORT_1A;
out port RXD = XS1_PORT_1B;

void transmitter(out port TXD) {
 unsigned byte, time;
 timer t;

 while (1) {

  /* get next byte to transmit */
  byte = getByte();

  t :> time;

  /* output start bit */
  TXD <: 0;
  time += BIT_TIME;
  t when timerafter (time) :> void;

  /* output data bits */
  for (int i=0; i<8; i++) {
   TXD <: >> byte;
   time += BIT_TIME;
   t when timerafter (time) :> void;
  }

  /* output stop bit */
  TXD <: 1;
  time += BIT_TIME;
  t when timerafter (time) :> void;

 }
}

 

Competition and Scalability

FPGAs were born to some degree from a similar requirement of low-cost, high-performance, rapid design cycles. Unfortunately, compared to software design processes, FPGAs are hard to program and use. FPGA designers are all too familiar with the problems of timing closure and the way small changes in specification can cause large changes in mapping (and by implication, timing). In practice, these difficulties mean that the support and training costs for developers are extremely high. FPGA vendors find as a result that their businesses can be tough to scale – and are not a good solution for many entry-level developers such as hobbyists, hackers or students.

XMOS has realized that in order to create a scalable customer ecosystem, it needs to make use of the full benefits of software methodology. Beyond a high-performance architecture, the company has created a new language – XC – which is an extended subset of C (the chips can also be programmed in C and C++ though these languages have no native access to concurrency primitives or ports). XMOS has chosen to open-source the XC tool-chain, numerous example interfaces (SPI, I2C, Ethernet, AVB, USB etc), and numerous PCB designs – and make them freely available for use by designers and developers. This – coupled with building a community website at http://www.xcore.com – is a critical element to encouraging communities of users and customers to form around the technology – to collaborate on improving state of the art technology and to provide a forum to explore new ideas – and potentially start new projects or businesses.

Conclusion

XMOS represents a shift in the way new electronic products can be created: with little investment and with a fast time-to-market. This makes it highly appealing not only for established players but also for startups. XMOS is definitely one to watch over the next few years – and is probably the most exciting of the group of fabless semiconductor companies rapidly approaching IPO.

  One Response to “An introduction to XMOS — an open hardware platform”

  1. [...] was recently asked to guest blog post on XMOS at FutureChips. Just a quick note here to say – head over and have a read. FutureChips is a blog run by Dr [...]

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